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    Enhancing Memory Capacity on the Raspberry Pi 2040 (RP2040)

    With a keen interest in tinkering, Dmitry Grinberg set out to expand the limited RAM capacity of his Raspberry Pi 2040 (RP2040). Originally, the board was equipped with just 264kb of on-board SRAM. Despite the chip’s capability to handle up to 16MB of off-flash memory through a QSPI bus, it lacked memory mapping functions. However, Dmitry ingeniously navigated this by utilizing the XIP (Execute in Place) mode and mapping 8MB of external QSPI RAM into the chip’s address space.

    Operating in XIP mode permits the RP2040 to fetch data from an external chip when needed and store it in the RP2040 caches mapped at 0x10xxxxxx. It should be noted that the RP2040 is limited to read and execute operations in XIP mode. To kickstart the process, Dmitry’s initial action involved transferring data from persistent storage to RAM during boot. Achieving this required the deployment of a dual-OR gate IC, an inverter, and two resistors to toggle the nCS pin, responsible for selecting between flash and RAM. A primary bootloader was then tasked with copying the program from flash to RAM, configuring XIP mode, and initiating a secondary loader.

    While progress was being made, obstacles emerged. Notably, the RP2040’s GPIO IP block experienced difficulty in resetting effectively, leading to the nCS pin failing to revert to selecting flash post-reset. Dmitry managed to resolve this by employing an I2C IO expander to gain control over the pin’s behavior.

    Subsequently, the challenge arose when attempting to write back changes to RAM during cache flushing. Dmitry tackled this by making use of the Memory Protection Unit (MPU). Normally, writing to 0x10xxxxxx would trigger cache line flushing, but by designating that region as read-only, the MPU could detect a hard fault upon any writing attempt. The fault handler then emulated the write instruction and proceeded with cache line flushing. Despite the apparent simplicity at a macro level, ARMv6M offers 127 distinct write instructions, translating to a significant performance concern. Remarkably, Dmitry managed to achieve an impressive clock rate of 36 Mbit/s for the memcpy function, rendering it a viable solution amid the challenges.

    Dmitry generously shared his revolutionary code for download on his website under the BSD-2 license. This gesture allows others to delve into the possibilities of leveraging a substantial amount of RAM on the RP2040 microcontroller. Such an innovative strategy unveils a plethora of imaginative opportunities. While not the inaugural emulator for the RP2040, the partial ARMv6 emulation represents a noteworthy feat, as evidenced in this RISC-V emulator.

    Image Source: nataliajakubcova @ Shutterstock

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